Visualizzazione dei post da agosto, 2018


Amiga 600 with Gayle ver.1, VHDL code to implement PAL chip (XU1)

This article is specific to the Amiga 600, so the chip designations, addressing and all the rest are related to this system, even when not explicitly indicated. Gayle is the custom chip that, among many other things, controls the ATA (IDE) port. There are two versions identified by the following chip numbers: Version 1: 391155-01 Version 2: 391155-02 As far as I could understand, the only difference between the two is the lack (incomplete? Erroneous?) of support for the ATA port in the first version: in detail, version 391155-01 needs an external logic to generate the IDE_CS1 and IDE_CS2 signals, which are needed to control an IDE hard disk. In addition, the external logic controls the RTC_CS (Clock Port 1 selection), SPARE_CS (Clock Port 2 selection) and NET_CS (Arcnet chip selection) signals. Obviously these are also directly handled in the second version of Gayle. In the Amiga this logic is implemented by the XU1 chip, a PAL16L8B, which is a programmable logic th